1. Technical Field
Various embodiments relate to an EM (Emission) signal control circuit, an EM signal control method, and an organic light emitting display device.
2. Related Art
Various types of electronic apparatuses including a mobile phone, a tablet PC, a notebook and so forth use a flat panel display (FPD) device. Examples of the FPD are a liquid crystal display (LCD) device, a plasma display panel (PDP) device, an organic light emitting display device (OLED), and an electrophoretic display (EPD) device.
Among the flat panel display devices, the organic light emitting display device is a spontaneously light emitting device capable of displaying images through light-emission of an organic light emitting diode by using the re-aggregation of the hole and the electron. The organic light emitting display device has characteristics of high-speed response and low power consumption. The organic light emitting display device shows an excellent viewing angle due to the use of the spontaneous light emitting element. Therefore, the organic light emitting display device draws attention as the next-generation flat panel display device.
An organic light emitting display device according to the related art has plural pixels disposed on a panel. Each of the plural pixels includes an organic light emitting diode (OLED) element and plural transistors each configured to apply currents to the organic light emitting diode element. Applied to the transistors of the respective pixels are a scan signal, a data signal, and an EM signal for controlling turn-on/off of the OLED element.
FIG. 1 is a configuration diagram illustrating a shift register and an EM signal control circuit included in an organic light emitting display device according to a related art. As shown in FIG. 1, the organic light emitting display device includes shift registers SR1 and SR2 and an EM signal control circuit INV coupled to the shift registers SR1 and SR2.
As illustrated in FIG. 1, the shift registers SR1 and SR2 generate scan signals Scan1 and Scan2 by using gate electrode power voltages G1VGH, G1VGL, G2VGH, and G2VGL, gate electrode start voltages G1VST and G2VST, and clock signals G1CLK1 to G1CLK4 and G2CLK1 to G2CLK4. The EM signal control circuit INV generates an EM signal EM by using emission power voltages EVGH and EVGL, the clock signal G1CLK2, and the scan signal Scan1.
FIG. 2 is a configuration diagram illustrating an EM signal control circuit according to a related art, and FIG. 3 is a waveform diagram illustrating respective signals according to the operation of the EM signal control circuit of FIG. 2. It is assumed hereinafter that a voltage of a first emission power source EVGH and a voltage of a first gate power source GVGH are respectively 14V and a voltage of a second emission power source EVGL and a voltage of a second gate power source GVGL are respectively −6V. Further, it is assumed that a set signal SET and a reset signal RESET are a low voltage level of −6V and a high voltage level of 14V, respectively.
Referring to FIGS. 2 and 3, the scan signal Scan1 of −6V is applied as the set signal SET to a QB node during a time section “t1”. Due to the application of the set signal SET during the time section “t1”, a voltage level of −6V is generated on the QB node and turns on a transistor T11, and the first emission power source EVGH is output as the EM signal EM through an output node NOUT. As the voltage level of −6V on the QB node also turns on a transistor T13, a voltage level of the first gate power source GVGH (i.e., a voltage level of 14V) is generated on a Q node, and thus a transistor T12 is turned off. Accordingly, as illustrated in FIG. 3, the first emission power source EVGH of 14V having the opposite level to the set signal SET of −6V is output as the EM signal EM during the time section “t1”.
Next, during a time section “t2”, a clock signal CLK2 of −6V is applied as the reset signal RESET to a gate electrode of a transistor T14, and the set signal SET of 14V is applied to the QB node. Accordingly, the transistor T14 is turned on and a voltage level of −6V is generated on the Q node. Therefore, the transistor T12 is turned on and the second emission power source EVGL of −6V is output as the EM signal EM. At this time, the voltage level of −6V on the Q node is maintained by a capacitor C. Therefore, the voltage level of the EM signal EM stays to −6V because of the voltage level of −6V maintained by the capacitor C despite periodical application of the reset signal RESET after the time section “t2”.
An organic light emitting display device according to the related art is capable of adjusting the brightness of a panel according to an external illuminance in order to improve power consumption and image quality under a low-illuminance circumstance. Such brightness adjustment may be implemented by a data voltage applied to the panel or by the EM signal EM generated as described above. That is, the turn-off time section of the respective pixels may be adjusted by adjusting the turn-on time section of the EM signal EM (e.g., the time section “t1” described with reference to FIG. 3). Such drive is referred to as an EM duty drive.
FIG. 4 is a waveform diagram illustrating respective signals according to the EM duty drive of the EM signal control circuit according to a related art.
Referring to FIGS. 2 and 4, the set signal SET of −6V is applied to the QB node during the time section “t1”, as described above. Therefore, the transistor T11 is turned on, and the first emission power source EVGH of 14V is output as the EM signal EM through the output node NOUT.
Next, during a time section “t2”, the voltage level of the EM signal EM is maintained to 14V in order to keep the organic light emitting diode element turned off for a predetermined time. To this end, the set signal SET and the reset signal RESET both having a voltage level of 14V are applied to the EM signal control circuit of FIG. 2.
However, in the case of keeping both of the set signal SET and the reset signal RESET to the voltage level of 14V, both of the transistor T11 and the transistor T12 of FIG. 2 are turned off and thus the output node NOUT is floated. Accordingly, the normal output of the EM signal EM through the output node NOUT cannot be secured during the time section “t2”.
During a time section “t3”, the reset signal RESET of −6V is applied to the transistor T14 and thus the transistor T12 is turned on. Therefore, the voltage level of the EM signal EM is −6V. After the time section “t3”, the voltage level of the set signal SET should be kept to 14V, and the voltage level of the EM signal EM should be kept to −6V regardless of the application of the reset signal RESET.
However, a threshold voltage of the transistor T11 is susceptible to change by a process condition of the transistor while manufacturing the organic light emitting display device, change of external temperature while driving the organic light emitting display device, deterioration of the transistor, and so forth. Therefore, despite the voltage level (i.e., 14V) of the set signal SET applied to the QB node of FIG. 2, the voltage level of the EM signal EM erroneously rises during a time section “t4” or a time section “t6” as illustrated in FIG. 4 due to the threshold voltage change of the transistor T11.
Accordingly, what is needed is an EM signal control circuit capable of preventing the floating of the output node NOUT during the time section “t2” and the voltage level change of the EM signal EM during the time section “t4” or the time section “t6” discussed with reference to FIG. 4.